Prescription: DE600 Digital Electronics

Aim of Module	To enable students to develop a knowledge of the operation of digital electronic circuits used in computer and Information Technology equipment.
Credits	7
Student Learning hours	70
Content Revised	pre 1996
Prescription Expiry Date	Nov 2007

Level and Assessment Schedule
Topics	Highest Skill Level	Suggested Assessment Percentage
1 Number systems	C	10
2 Boolean Algebra	A	10
3 Karnaugh Map	C	10
4 Basic logic gates	C	20
5 Fixed logic circuits	A	25
6 Synchronous logic	A	25
		100

The Student Will

1	Number systems

>	Understand the structure of number systems, their application and conversion from one to another. This will include:
C	1.1	Explain the structure of the following number systems:
		-binary
		-octal
		-decimal
		-hexadecimal
A	1.2	Add and substract values in these number systems including complementary arithmetic.
A	1.3	Convert from one number system to any other.
C	1.4	Explain the application of the number systems.

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2	Boolean Algebra

>	Understand the basic principles of Boolean algebra and its use in the design of logic circuits. This will include:
R	2.1	Demonstrate, using simple examples, that logical processes may be plotted in the form of a truth table.
C	2.2	Demonstrate, using simple switch circuits, the following Laws of Boolean algebra:
		1 A.B = B.A
		2 A.l = A
		3 A.O = O
		4 A.A = A
		5 A.A = O
		6 A = A
		7 A+B = B+A
		8 A+l = 1
		9 A+O = A
		10 A+A = A
		11 A.B.C = A.(B.C.)= (A.B). C
		12 A+B+C = (A+B)+C=A+(B+C)
		13 A- (B+C) = A.B + A.C.
		14 A+B.C = (A+B).(A+C)
A	2.3	Derive, using truth tables, the Boolean expression for given systems.
C	2.4	Simplify using Boolean algebra, the expressions derived in 2.3.
A	2.5	Verify the circuits that can be built from the simplified expressions obtained in 2.4.
	2.6	Convert one Boolean expression to another by the use of De Morgan’s Theorem.

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3	Karnaugh Map

>	Understand the structure and use of a Karnaugh map to simplify a Boolean expression. This will include:
R	3.1	The technique of drawing a Karnaugh map is described.
A	3.2	A Boolean expression is simplified by the use of a Karnaugh map.
	3.3	The solution of the Karnaugh map is verified by using the techniques described in paragraph two.

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4	Basic logic gates

>	Understand the symbols, truth tables and Boolean expressions for the basic logic gates. This will include:
R	4.1	Sketches the logic circuit symbol for AND, OR, NOT, NAND, NOR and XOR gates.
C	4.2	Constructs the truth tables for these gates.
C	4.3	Describes these gates with the aid of simple diagrams.
A	4.4	Demonstrates the configuration of a NAND gate and a NOR gate as an inverter.

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5	Fixed logic circuits

>	Understand that basic gates can be used to create fixed logic functions.
A	5.1	Design a half adder from basic principles and show how it can be simplified by the use of a XOR.
A	5.2	Design a full adder from two half adders and explain the limitation of the half adder.
A	5.3	Prove that a comparator is logicaly equivalent to the inversion of a XOR. by the use of Boolean algebra.
C	5.4	Explain the operation of a decimal to BCD encoder.
	5.5	Explain the operation of a BCD to decimal decoder.

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6	Synchronous logic

>	Understand the need for synchronous logic, the basic circuit elements of registers and counters and how they are constucted. This will include:
C	6.1	Constructs a simple RS bistable using NAND or NOR gates and derives its truth table.
	6.2	Constructs a gated RS bistable using NAND or NOR gates, derives its truth table and explains its action.
	6.3	Constructs a D type bistable, derives its truth table and explains its action.
	6.4	Identifies the need for a JK bistable.
	6.5	Constructs a JK bistable, derives its truth table and shows how it satisfies the need of 6.4.
	6.6	Identifies the need for a Master-Slave bistable circuit.
	6.7	Identifies the circuit symbols for the simple RS bistable devices.
R	6.8	Describes at least one application for each of the simple RS bistable devices.
6.1.1	COUNTERS
>	Understand the need for counting circuits and their operation. This will include:
R	6.1.2	States that a JK bistable with appropriate input connections can be used as a divide-by-two counting device.
	6.1.3	States that counters may be synchronous or asynchronous and compares the two in terms of speed of operation, ripple through delay and dynamic hazard.
	6.1.4	Sketches the circuit diagram of a divide by sixteen counter in the synchronous and asynchronous forms.
A	6.1.5	Demonstrates, using the asynchronous counter of 6.1.3 and a truth table including the Q and Q outputs, that it may be used to count up from O to 15 and down from l5 to O.
C	6.1.6	Demonstrates using the counter of 6.1.4 how, with additional gating, the count may be curtailed at any desired value.
6.2.1	REGISTERS
>	Understands the need for registers and their operation. This will include:
R	6.2.2	Sketches the simple logic diagram of a four bit register showing:
		-serial input
		-parallel inputs
		-clock input
		-serial and parallel outputs
C	6.2.3	Describes the operation of the register in 6.2.1 and describes one application of the circuit.
R	6.2.4	Sketches the logic diagram of a four bit register which incorporates the following facilities:
		-serial input,
		-parallel inputs
		-clock inputs
		-shift mode controls
		-left and right shift capability.
C	6.2.5	Describes the operation of the circuit of 6.2.4
R	6.2.6	States that registers of both types are commercially available in TTL and CMOS form.
C	6.2.7	Compares the performance of TTL and CMOS registers in terms of speed and flexibility of operation.

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Note
>	Topics 4-6 inclusive must involve practical work.